Learning Objectives

By the end of this lesson, the technician will be able to:

• Objective 1 (Cognitive/Understanding): Decode I/O addresses on the major platform conventions (rack/slot/point and tag-based), and translate fluently between a drawing's address, a terminal number, and a physical module point.
• Objective 2 (Cognitive/Understanding): Explain the electrical isolation layers between field circuits and the controller — optical isolation, isolated commons/groups, interposing relays, and fusing — and what each layer protects.
• Objective 3 (Field/Practical): Safely verify a single I/O point end-to-end (field device → terminal → module point → address) using the channel LED, a DMM, and the drawing set, without program modification.

Field Scenario

The Swap That Killed Two Channels: A second-shift technician replaces a failed solenoid on a hopper gate. The new solenoid is "the same valve" — except the failed one was a 24 VDC coil and the replacement pulled from stores is 120 VAC. He lands it on the same output point. The coil buzzes once; the channel never works again. He moves the wire to a spare point on the same module to "get the line running." That point dies too. Now the work order says: output module failing, channels dying one by one — replace module, suspect PLC going bad.

You read it differently: channels don't die one by one from age — they die one by one from what's being connected to them. The module is a 24 VDC transistor output module; a 120 VAC coil on a DC transistor point is a dead transistor, every time. The module did its deeper job, though: its optical isolation kept the abuse on the field side, and the backplane and CPU never felt it. Two burned channels, zero processor damage — the isolation architecture working exactly as designed.

The fix is the module (two points are gone), the correct 24 VDC solenoid, and the real lesson in the CMMS notes: the drawing's I/O list specifies the voltage class of every point for a reason. An address tells you where a point lives; the drawing tells you what's allowed to be wired to it. Both halves of that sentence are this lesson.

Concept Overview

Addressing: The Map Between Logic and Copper

Every field wire ends at a module point, and every module point has a logical address the program uses. Two conventions dominate:

Fixed/rack-based addressing (legacy and small platforms). The address encodes the physical location directly. Allen-Bradley PLC-5/SLC-500 style: I:3/07 — Input, slot 3, point 07; O:4/12 — Output, slot 4, point 12. Siemens classic style: %I0.3 / %Q0.3 (I = input, Q = output, byte.bit). The address is the location: change the slot, and every reference changes.

Tag-based addressing (modern platforms, e.g., ControlLogix/CompactLogix, modern Siemens). The program references named tags — Hopper_Gate_Sol, Conveyor_Run_PB — and a configuration table maps each tag to physical points like Local:4:O.Data.12 (local chassis, slot 4, output data, bit 12) or remote equivalents. Two consequences for the technician:

• The HMI and program speak in names; the panel speaks in slots and points. The I/O mapping table in the program (read-only access) or the drawing set's I/O list is the dictionary between them.
• A tag can be re-mapped without rewiring — which is why the drawings and the live configuration can disagree after undocumented changes. The verification habit in Section 6 exists because of exactly this.

The universal skill is the translation chain: device tag on the machine → wire number → terminal block → module/slot/point → logical address → HMI name. Every PLC diagnosis crosses this chain at least once; Lesson 7.1's mapping exercise built it, and this lesson makes it precise.

Isolation: The Layers That Keep the Field's Violence Out of the Controller

Field circuits live a rough electrical life — inductive kicks from coils, shorts, miswires (the Field Scenario), lightning-adjacent transients. Several deliberate layers stand between that world and the logic:

Optical isolation (built into I/O modules). Inside nearly every discrete I/O channel, the field signal drives an LED that shines across a physical gap onto a phototransistor — light crosses, electricity cannot. Field faults burn the field side of the channel and stop there. This is why the Field Scenario cost two channels instead of a processor.

Isolated commons and grouping. Module points are organized into groups sharing a common terminal. The wiring diagram's group boundaries matter operationally: one group can serve 24 VDC while another serves a different source — but only if the commons are truly separate. Tying commons from different supplies together (a classic miswire) creates circulating paths and ghost signals. Isolated modules (per-point or per-group isolation) exist precisely for mixed-source panels.

Interposing relays. When a field load exceeds the module channel's rating (current, voltage class, or inrush), the module drives a small interposing relay coil, and the relay's contacts switch the real load. The relay is a sacrificial, replaceable isolation layer — and the correct answer whenever someone proposes hanging a big contactor coil or any AC load on a DC transistor point. Coil suppression (diode/RC across the coil) belongs on every interposing relay; unsuppressed coils kick transient spikes back into the output channel and shorten its life (noise discipline per Lesson 6.9).

Fusing — module, group, and point level. Some modules carry internal electronic protection or per-group fuses; many panels add external fuse terminal blocks per point. Two field facts: a blown point fuse perfectly mimics a failed channel (output LED on, load dead — check the fuse before condemning the module), and electronic-protected outputs may auto-recover after a short clears, producing maddening intermittents traceable to a chafed wire.

Field power segregation. Lesson 7.1's rule extended: the rack supply powers logic; field supplies power devices through the modules. Drawings show separate supplies per voltage class and often per machine zone — so one shorted solenoid trips one field circuit's protection and takes down one zone's outputs (Lesson 7.2's scenario), not the controller.

How the Principle Works: Reading the I/O Drawing Like a Schematic

The I/O wiring drawing is the legal record of the translation chain and isolation design. The standard page layout (full drawing conventions in Module 10):

• Each module gets a sheet/zone: slot number, module part number, point list.
• Per point: the address, the wire numbers, the terminal block numbers, the device tag it serves, and the fuse designation if fused per point.
• Per group: the common terminal and which field supply feeds it (supply designations like PS-2/+24V-2 trace back to the power distribution sheet).
• Voltage class is stated per module/group — the line of defense the Field Scenario crossed.

Worked translation: drawing shows LS-204 — wire 4137 — TB4-137 — Slot 3 IN-07 — I:3/07 — fuse FU-137 — common GRP0 (PS-3, 24VDC). From this one line a technician knows: where to measure (TB4-137), what to expect (24 VDC class), which LED to watch (slot 3, point 7), what the program calls it (I:3/07 or its mapped tag), which fuse can fake a failure (FU-137), and which supply outage would take this point's whole group down (PS-3).

Addressing & Isolation Reference Matrix

Field Application Checklist: End-to-End Verification of a Single I/O Point

Boundaries: panel work under electrical safe-work rules (Lessons 1.5/5.1). This procedure is measurement and observation only — no forces, no program edits, no mode changes (Lesson 7.6 governs software boundaries). Actuating field devices requires the machine in a safe state and operations' knowledge; LOTO (Lesson 1.2) whenever hands enter the motion envelope.

1. Pull the drawing first. Write out the full translation chain for the point (device tag → wire → terminal → slot/point → address → fuse → group/supply). Working from memory of "where it usually is" is how the wrong point gets measured.
2. Confirm voltage class before any connection or measurement plan — module family and group voltage from the drawing. (The Field Scenario check: is what's wired here allowed to be here?)
3. Inputs — verify upstream to downstream: actuate the device safely → device output at its terminals (per Lesson 6.2 for sensor types) → voltage at the panel terminal block → channel LED follows → (if laptop attached, read-only) input image bit follows. The first place the signal disappears names the failed link.
4. Outputs — verify downstream from the decision: channel LED commanded on (by normal machine action — not by forcing) → voltage at the module point → through the fuse → at the load terminals → load responds. LED-on-but-dead-terminal = module point or its fuse; live-terminal-but-dead-load = wiring or device.
5. Respect the group: if several points misbehave together, stop point-chasing and check what they share — common terminal, group fuse, field supply (the matrix's last row).
6. Check interposing layers where present: the relay is a second LED and a second set of terminals in the chain — verify both sides.
7. Document the verified chain and reconcile any drawing discrepancy through the site's redline process (Lesson 10.9). An I/O list correction is cheap; the miswire it prevents is not.

Knowledge Check

Source List

• Rockwell Automation / Allen-Bradley — Logix5000 Controllers I/O and Tag Data and SLC-500 addressing references; 1769/1756 I/O module wiring diagrams (groups, commons, isolation)
• Siemens — SIMATIC S7 addressing and module data manuals
• IEC 61131-2 — programmable controller equipment and isolation requirements
• NFPA 79 — Electrical Standard for Industrial Machinery (control circuit protection and wiring practices)
• Frank Petruzella, Programmable Logic Controllers (McGraw-Hill) — addressing conventions and I/O interfacing chapters